1. Field of the Invention
The present invention relates to a sampling inspection estimating method, a sampling inspection estimating apparatus, and a sampling inspection estimating program. More particularly, the invention relates to a method of estimating a sampling inspection in a process of manufacturing a semiconductor device, a sampling inspection estimating apparatus for the sampling inspection, and a sampling inspection estimating program for the sampling inspection.
2. Related Art
The characteristics of a semiconductor integrated circuit have close relation with dimensions of a pattern formed in each of processes and a layer alignment shift. Therefore, the process of manufacturing a semiconductor integrated circuit includes a inspection process of monitoring whether dimensions and a layer alignment shift are controlled or not. Since the number of patterns formed is extremely large and it is difficult to monitor all of the patterns in the inspection process, a sampling inspection, not a 100% inspection, is performed.
In a general semiconductor integrated circuit manufacturing process, a collection of a plurality of semiconductor chips formed in a plurality of silicon wafers or a single wafer is manufactured as a production lot. Therefore, in a sampling inspection, a predetermined number of wafers are selected from a production lot, and the positions and the number of chips to be inspected are selected from the selected wafers.
However, since the manufacturing process capability changes with time, in the case where a sampling inspection is conducted by using a predetermined sampling plan, there is a possibility that a risk of regarding a non-defective lot as a defective lot (hereinbelow, called “producer's risk”) and a risk of overlooking a defective lot (hereinbelow, called “consumer's risk”) varies.
To address the problem, a method of changing the sampling plan (for example, the sample size or sampling position) may be employed.
As general sampling inspections, an attribute sampling inspection of theoretically generating an operating characteristic curve (hereinbelow, called “OC curve”) based on a hypergeometric distribution and calculating an a risk and a β risk (see H. F. Dodge and H. G. Roming: “Single Sampling and Double Sampling Inspection Tables”, The Bell System Technical Journal, pp. 1-61 (1941), hereinbelow, called “non-patent document 1”) and a sampling inspection by variables for theoretically generating an OC curve based on a noncentral t distribution in which normal population is assumed and calculating an α risk and a β risk (see Military Standard: “Sampling Procedures and Tables for Inspection by Variables for Percent Defective: MIL-STD-414” (1957), hereinbelow, called “non-patent document 2”) are known. In a general inspection process, the sampling inspection disclosed in the non-patent document 1 or 2 is performed on a plurality of sampling plans.
However, since the precondition of the sampling inspections of the non-patent documents 1 and 2 is random sampling, an OC curve for a general semiconductor integrated circuit sampling inspection cannot be generated.
Since the precondition of the sampling inspection by variables of the non-patent document 2 is that the population follows a normal distribution, the OC curve of a nonnormal distribution of the population cannot be generated.
On the other hand, a method of generating an OC curve empirically by 100% inspection data in actual products in place of theoretically generating an OC curve is considered.
It is however difficult to empirically generate the OC curve for the following two reasons. A first reason is that, since the horizontal axis for the OC curve indicates percent defective (that is, the fraction defectives existing in a production lot) and the vertical axis indicates the acceptance probability corresponding to the percent defective, many production lots have to be inspected to estimate the percent defective. The second reason is that although the probability of acceptance/rejection of lots at each percent defective has to be calculated by controlling the percent defective in order to empirically obtain the acceptance probability as a function of defectives, it is difficult to control the percent defective.
Specifically, in the conventional semiconductor integrated circuit manufacturing process, when the precondition of random sampling or the precondition of the normal population is not satisfied, the sampling inspection is not accurately estimated. Consequently, by performing the inspection process using the sampling inspection determined empirically by technical experts, there is a probability that an α risk and a β risk exceeding an acceptable range occur (see U.S. Pat. No. 6,868,299).